This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-194742, filed Jun. 28, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to an electric fuse whose dielectric breakdown resistance is controlled by injecting impurities into an insulating film of a capacitor structure, and a method for manufacturing the same, and particularly relates to an electric fuse for use in redundancy technique.
In recent years, as the technologies for manufacturing semiconductor devices are advancing, the semiconductor devices have been more miniaturized and highly integrated on a large scale. However, with alternation of generations of the integration level, it has become difficult to keep the manufacturing yield the same as that of the previous generation. The redundancy technique has been noticed as a method for improving the manufacturing yield of semiconductor devices. In this technique, a fuse element is provided inside a semiconductor device in order to relieve a semiconductor element that becomes partially defective. If a defect occurs in a semiconductor element of a chip, a fuse element corresponding to the defective portion is cut and the semiconductor element is replaced with a spare, so that the yield of the overall chip can be improved.
A laser fuse is a kind of the fuse elements as mentioned above. In the laser fuse, a metal wiring layer is melted by laser irradiation (laser blow), so that information corresponding to the defective portion can be written in the laser fuse. However, when the laser fuse is used, even if a new defect occurs in downstream processes after the laser blow (for example, a packaging process), the new defective portion cannot be released. In this case, since the chip, which will finally be disposed of as a defective product, is subjected to the laser blow, the cost will be wasted.
In contrast, with an electric fuse which can be electrically cut or short-circuit, a defective element can be replaced with a spare even after completion of the packaging process. Therefore, the manufacturing yield can be improved as that in the case where the laser fuse is used. Further, since the chip, which becomes defective in the packaging process, is not replaced with a spare, the electric fuse is efficient and effective redundancy means. An anti-fuse using a capacitor structure is a kind of the electric fuse. With the anti-fuse, a high voltage is applied to the capacitor structure (fuse capacitor) to break a dielectric film, thereby electrically short-circuiting the fuse capacitor, so that information can be written in the anti-fuse.
A structure of the anti-fuse and a method for manufacturing the same will be described with reference to FIGS. 1A to 1C. FIGS. 1A to 1C are cross-sectional views sequentially showing the steps for manufacturing an anti-fuse having a MOS structure.
First, as shown in FIG. 1A, an element isolating region 11 is formed in a circuit region A1 and a peripheral region A2 of a silicon substrate 10. The circuit region is a region where essential circuit elements, such as MOS transistors, are to be formed, and the peripheral region is a region where anti-fuses are to be formed. A gate insulating film 12 and a polycrystalline silicon film 13a are formed on the silicon substrate 10.
Then, as shown in FIG. 1B, a tungsten film 13b is formed on the polycrystalline silicon film 13b. 
Thereafter, as shown in FIG. 1C, the polycrystalline silicon film 13a and the tungsten film 13b are patterned to form gate electrodes 13.
Subsequently, in the circuit region A1, impurity diffusion layers to serve as source and drain regions (not shown) are formed in the silicon substrate 10. As a result, a MOS transistor is formed in the circuit region A1. At the same time, an anti-fuse, having a capacitor structure including the gate electrode 13, the gate insulating film 12 and the silicon substrate 10, is formed in the peripheral region A2.
In the anti-fuse having the MOS structure as described above, a high voltage is applied across the gate electrode 13 and the silicon substrate 10, resulting in dielectric breakdown of the gate insulating film 12 to bring about a conduction state, so that information can be written in the anti-fuse.
The anti-fuse is also used, for example, when a defective memory cell is replaced with a redundant memory cell in a DRAM (Dynamic Random Access Memory), which has become highly integrated on a large scale. FIGS. 2A to 2C are cross-sectional views sequentially showing steps for manufacturing a DRAM in which a double-sided cylinder type stack capacitor is used as a cell capacitor.
First, as shown in FIG. 2A, an element isolating region 11 is formed in a memory cell array region A1 and a peripheral region A2 of a silicon substrate 10 by means of the conventional art. Then, a gate insulating film 12 is formed on the silicon substrate 10. Thereafter, a gate electrode 13 is formed on the gate insulating film 12 in the memory cell array region A1. Further, an impurity diffusion layer 14 is formed in that portion of the silicon substrate 10 that is located between the adjacent gate electrodes 13, with the result that a cell transistor is formed. In the peripheral region A2, an impurity diffusion layer 14, to be connected to one of the electrodes of the anti-fuse, is formed in the semiconductor substrate 10. An interlayer insulating film 15 for covering the cell transistor is formed on the silicon substrate 10. Subsequently, in the memory cell array region A1, a bit line 17 connected to the drain region of the cell transistor is formed in the interlayer insulating film 15. Thereafter, an interlayer insulating film 16 is formed on the interlayer insulating film 15. Contact plugs 18 connected to the source region of the cell transistor and the impurity diffusion layer 14 of the peripheral region A2, and capacitor lower electrodes 19 of double-sided cylinder type connected to the contact plugs 18 are formed.
Then, as shown in FIG. 2B, a capacitor insulating film 20 and a capacitor upper electrode 21 are successively formed on the capacitor lower electrode 19. The resultant structure is patterned to a desired wiring pattern. Through this process, a cell capacitor and a fuse capacitor are formed respectively in the memory cell array region A1 and the peripheral region A2.
Thereafter, an interlayer insulating film 22 for covering the cell capacitor and the fuse capacitor and a metal wiring layer (not shown) is formed by the conventional technique, so that the structure shown in FIG. 2C is completed.
In the case of the aforementioned anti-fuse in the DRAM, a high voltage is applied across the capacitor lower electrode 19 and the capacitor upper electrode 21, thereby causing dielectric breakdown of the capacitor insulating film 20 to write information into the anti-fuse.
In general, as described above, the anti-fuse is formed in the process for forming another circuit element, utilizing the structure of the circuit element, for the following reason. The anti-fuse is a mere backup element for the essential function of the semiconductor device. If a manufacturing process for forming only an anti-fuse is added, the overall process will be complicated and troublesome, resulting in nothing but an increase in manufacturing cost.
Thus, since the anti-fuse is formed by utilizing the structure of another circuit element, it has the same characteristics as those of the circuit element. In the above example, the anti-fuse has the same characteristics as those of the gate portion of the MOS transistor or the cell capacitor.
However, the characteristics required for the MOS transistor or the cell capacitor are naturally different from those required for the anti-fuse. More specifically, the MOS transistor and the cell capacitor require a high dielectric breakdown resistance to ensure the reliability as a circuit element. To the contrary, the anti-fuse requires a low dielectric breakdown resistance, so that the fuse can be broken with the lowest possible voltage.
In other words, the same capacitor structures produced by the same process are required to achieve both a dielectric breakdown resistance that can at least ensure the performance as a MOS transistor or a cell capacitor and a dielectric breakdown resistance that can ensure the function of an anti-fuse to write information at a low voltage.
For example, assumed that the limit value of the dielectric breakdown resistance, which ensures the performance of the anti-fuse, is DV1, and the lowest dielectric breakdown resistance, which ensures the performance of the MOS transistor or the cell capacitor, is DV2. In this case, the dielectric breakdown resistances of the capacitor structures must be set within the range between an upper limit of DV1 and a lower limit of DV2.
As described above, the conventional anti-fuse must be developed under limited process conditions.
Further, in the early stages of the development of a DRAM, the cell capacitor does not have performance that can ensure the reliability. As the development advances, the performance is approaching to the objective. On the other hand, the technical development of an anti-fuse is started only in the later stages of the development at which the cell capacitor reaches the objective performance. For this reason, the period of development of the DRAM is inevitably long.
A semiconductor device according to an aspect of the present invention comprises:
capacitor structures, each having a first gate insulating film formed on a semiconductor substrate of a first conductivity type, and a first gate electrode formed on the first gate insulating film; and
electric fuse elements, each having a second gate insulating film formed on the semiconductor substrate and having an impurity concentration higher than that of the first gate insulating film, and a second gate electrode formed on the second gate insulating film, wherein information is written in the electric fuse element depending on whether the second gate insulating film is dielectrically broken down, and a writing voltage of the electric fuse element is determined by dielectric breakdown resistance of the second gate insulating film which depends on the impurity concentration of the second gate insulating film; and
an impurity diffusion layer of a second conductivity type, which is formed in at least a portion of the semiconductor substrate, the impurity diffusion layer being paired with the second gate electrode and serving as one electrode of the electric fuse element.
A method for fabricating an electric fuse according to an aspect of the present invention comprises:
forming an insulating film on a first electrode;
forming a second electrode on the insulating film; and
injecting by ion injection an impurity into at least a portion of the insulating film or passing the impurity therethrough, thereby controlling dielectric breakdown resistance of the insulating film to set a writing voltage.